In DRAM, which is one type of semiconductor storage device, a memory cell composed of a single transistor and a single capacitor is disposed at the intersection of a word line and a bit line that intersect with each other. Layout systems in DRAM memory cells are classified as folded bit line systems and open bit line systems (see Japanese Laid-open Patent Application No. 2004-80009). In a folded bit line system, two bit lines that are connected to a single sense amplifier are folded at the sense amplifier so as to be wired in the same direction, and the minimum theoretical area of the memory cell is 8F2 (4F×2F), wherein “F” is the minimum feature size (half the pitch of the word lines). In an open bit line system, two bit lines that are connected to a single sense amplifier are wired so as to extend in opposite directions on the sides of the sense amplifier, and the minimum theoretical area of the memory cell is 6F2 (2F×3F).
FIG. 23A through 23F shows an example of the layout of conventional DRAM having a cell area of 6F2. A plurality of active regions 13 is formed symmetrically about a line (FIG. 23A), and word lines 14 are wired in the Y direction at intervals of 1F (FIG. 23B). Cell contacts 18 are formed in the center portions and end portions of the active regions 13 (FIG. 23C). Bit line contacts (not shown) are formed directly above the cell contacts 18 of the central portions, and bit lines are wired so as to extend in the X direction in meandering fashion over the bit line contacts so as to avoid the cell contacts 18 of the end portions (FIG. 23D). Storage node contacts 24 are formed above the cell contacts 18 disposed at the end portions of the active regions 13 (FIG. 23E). The center positions of the storage node contacts 24 are offset from the center positions of the cell contacts 18, whereby the storage node contacts 24 are arranged at equal intervals in the X direction. Storage capacitors 28 are also formed directly above the storage node contacts 24 (FIG. 23F).
Japanese Laid-open Patent Application No. 2004-80009 discloses a structure of an integrated circuit memory element in which a landing pad is formed between a contact plug and a storage capacitor. This integrated circuit memory element comprises an interlayer insulating film that is formed on a substrate and has numerous storage node contact holes arranged linearly in one direction; storage node contacts that are embedded in the storage node contact holes; an insulating film that is formed on an interlayer insulating film and has numerous landing pad holes that are arranged nonlinearly in one direction and that expose the storage node contacts; landing pads that are embedded in the landing pad holes and connected to the storage node contacts; and storage capacitors connected to the landing pads. In this structure, since landing pads are formed between the contact plugs and the storage capacitors, the storage capacitors can be arranged in a zigzag pattern in a plane even when the contact plugs are aligned in the transverse and longitudinal directions of the plane.
The layout of conventional DRAM having the memory cell area of 6F2 shown in FIGS. 23A through 23F has a region in which the storage capacitors are not arranged in zigzag fashion on the plane, and the storage capacitors cannot be placed in a perfectly zigzag arrangement. Therefore, the storage capacitors cannot be packed at maximum density.
In the structure disclosed in Japanese Laid-open Patent Application No. 2004-80009, when the contact plugs are aligned in the transverse and longitudinal directions on a plane, the storage capacitors can be arranged in zigzag fashion and packed at maximum density merely by being arranged in zigzag fashion so as to be offset from each other. However, in such a case as when the contact plugs are originally arranged in zigzag fashion in the transverse and longitudinal directions, it is difficult to pack the storage capacitors at maximum density. Since the elliptical storage capacitors have an inadequate diameter in the minor axis direction, it is impossible to increase the capacity of the capacitors. Furthermore, when the lower electrode of an MIS (Metal Insulator Silicon) capacitor is composed of HSG-Si (Hemi-Sphericai Grained poly-Si), the HSG blockage margin cannot be adequately ensured, and the cylinder holes used by the storage capacitors become blocked with HSG-Si.